The present invention relates generally to the electrical, electronic, and semiconductor arts and, more particularly, to semiconductor devices.
Edge placement error is currently a limiting factor impeding semiconductor scaling to smaller nodes. Forming pillars with small critical dimensions is especially challenging because of limitations of currently used etching materials, and small pillars with critical dimensions sometimes fail.
A selective atomic layer deposition (sALD) process has been developing for use in integrated circuit fabrication. Selective atomic layer deposition deposits material directly on selected surface areas of a wafer on which it is desired to have the material. The selective atomic layer deposition process has a very limited material selection as only a few atomic layer deposition precursors will work with surfaces on which they are deposited. High temperature (e.g., >400 C) is required in many sALD processes, which makes it difficult to be applied in backend-of-the-line (BEOL) semiconductor manufacturing processes. Furthermore, selective atomic layer deposition has not shown a sufficient degree of freedom in material selection and growth rate differences compared to other processes to be widely adopted commercially.